VLSI M.tech Projects 2018-19

A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation

A Slack-based Approach to Efficiently Deploy Radix 8 Booth Multipliers

Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers


Design of Power and Area Efficient Approximate Multipliers

Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing

Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx

Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity

A Residue-to-Binary Converter for the Extended Four-Moduli Set {2n− 1, 2n+ 1, 22n+ 1, 22n+p}

Fast Energy Efficient Radix-16 Sequential Multiplier

DSP48E Efficient Floating Point Multiplier Architectures on FPGA

Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems

Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic

Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication

Design and Analysis of Multiplier Using Approximate 15-4 Compressor

Energy-Efficient Approximate Multiplier Design using Bit Significance-Driven Logic Compression

High Performance Parallel Decimal Multipliers using Hybrid BCD Codes

High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder

Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction

On the Implementation of Computation-in-Memory Parallel Adder

Optimal Design of Reversible Parity Preserving New Full Adder / Full Subtractor

Probabilistic Error Analysis of Approximate Recursive Multipliers

RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder

RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing

Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm

An Optimized 3x3 Shift and Add Multiplier on FPGA

Optimization of Constant Matrix Multiplication with Low Power and High Throughput

DLAU: A Scalable Deep Learning Accelerator Uniton FPGA

Reconfigurable Constant Multiplication for FPGAs

Efficient RNS Scalers for the Extended Three-Moduli Set (2n -1; 2n+p; 2n + 1)

Weighted Partitioning for Fast Multiplierless Multiple-Constant Convolution Circuit

Fault Space Transformation: A Generic Approach to Counter Differential Fault Analysis and Differential Fault Intensity Analysis on AES-like Block Ciphers

Probabilistic Error Modeling for Approximate Adders

Low Complexity and Critical Path based VLSI Architecture for LMS Adaptive Filter using Distributed Arithmetic

A Bit plane Decomposition Matrix Based VLSI Integer Transform Architecture for HEVC

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST s

LFSR-Based Generation of Multi cycle Tests

Design for testability of sleep convention logic

Reliability Enhancement of Low-power sequential circuits using reconfigurable Pulsed Latches

Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping

An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA

Probability-Driven Multibit Flip-Flop Integration With Clock Gating

Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

Design of high speed multiplier using Modified Booth Algorithm with hybrid carry look-ahead adder

Design of Reversible 32-Bit BCD Add-Subtract Unit using Parallel Pipelined Method

Low Power Reconfigurable Hilbert Transformer Design with Row Bypassing Multiplier on FPGA

Design of an optimized reversible bidirectional barrel shifter

Encryption Using Reconfigurable Reversible Logic Gate and Its Simulation in FPGAs

Design of Register File using Reversible Logic

A Heuristic for Linear Nearest Neighbor Realization of Quantum Circuits by SWAP Gate Insertion Using -Gate Look ahead

A Parallel Decimal Multiplier Using Hybrid Binary Coded Decimal (BCD) Codes

A Modified Partial Product Generator for Redundant Binary Multipliers

Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic

Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding

Low-Quantum Cost Circuit Constructions for Adder and Symmetric Boolean Functions

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

Design of reversible circuits with high testability

An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA

Logic Synthesis in Reversible PLA

Design for Testability of Sleep Convention Logic

Synthesis of Approximate Coders for On-chip Interconnects Using Reversible Logic

Fault Detection in Parity Preserving Reversible Circuits

Improved Synthesis of Reversible Sequential Circuits

Squaring in Reversible Logic using Zero Garbage and Reduced Ancillary inputs

A Pre-Optimization Technique to Generate Initial Reversible Circuits with Low Quantum Cost

Primitive components of Reversible Logic Synthesis

Reversible Circuit Synthesis Using Binary Decision Diagrams

An Efficient Approach to Design a Compact Reversible Programmable Logic Array

An Improved Factorization Approach to Reversible Circuit Synthesis Based on EXORs of Products of EXORs

Compressor Based 8x8 Bit Vedic Multiplier Using Reversible Logic

VLSI M.Tech Projects 2017

A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory

A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System

A Hybrid Frequency/Phase-Locked Loop for Versatile Clock Generation with Wide Reference Frequency Range

A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits

A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT

A Modified Partial Product Generator for Redundant Binary Multipliers

A Test-per-Cycle BIST Architecture with Low Area Overhead and No Storage Requirement

An Efficient Hardware Implementation of Canny Edge Detection Algorithm

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code

An Improved Signed Digit Representation Approach for Constant Vector Multiplication

Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach

Code Compression for Embedded Systems Using Separated Dictionaries

Concept, Design, and Implementation of Reconfigurable CORDIC

Design Methodology for Voltage-Scaled Clock Distribution Networks

Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs

Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories

Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m)

Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library

Logic Synthesis in Reversible PLA

Low-Power FPGA Design Using Memoization-Based Approximate Computing

Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units

LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter

On Efficient Retiming of Fixed-Point Circuits

Path Constraint Solving based Test Generation for Observability-enhanced Branch Coverage

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Self-Repairing Digital System Based on State Attractor Convergence Inspired by the Recovery Process of a Living Cell

Source Code Error Detection in High-Level Synthesis Functional Verification

Squaring in Reversible Logic using Zero Garbage and Reduced Ancillary inputs

Using Tweaks To Design Fault Resistant Ciphers

A High Throughput List Decoder Architecture for Polar Codes

Design and Analysis of Inexact Floating-Point Adders

Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers

Hybrid LUT/Multiplexer FPGA Logic Architectures

Low-Power Parallel Chien Search Architecture Using a Two-Step Approach

Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression

Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design

Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding

VLSI Design for Convolutive Blind Source Separation

A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler

A Generalization of Addition Chains and Fast Inversions in Binary Fields

A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications

A parallel radix-sort-based VLSI architecture for finding the first W maximum/minimum values

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability