VLSI B.tech Projects 2018-19

A 520k (18 900, 17 010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory

A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System

A Hybrid Frequency/Phase-Locked Loop for Versatile Clock Generation with Wide Reference Frequency Range

A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits

A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT

A Modified Partial Product Generator for Redundant Binary Multipliers

A Test-per-Cycle BIST Architecture with Low Area Overhead and No Storage Requirement

An Efficient Hardware Implementation of Canny Edge Detection Algorithm

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code

An Improved Signed Digit Representation Approach for Constant Vector Multiplication

Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach

Code Compression for Embedded Systems Using Separated Dictionaries

Concept, Design, and Implementation of Reconfigurable CORDIC

Design Methodology for Voltage-Scaled Clock Distribution Networks

Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs

Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories

Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m)

Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library

Logic Synthesis in Reversible PLA

Low-Power FPGA Design Using Memoization-Based Approximate Computing

Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units

LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter

On Efficient Retiming of Fixed-Point Circuits

Path Constraint Solving based Test Generation for Observability-enhanced Branch Coverage

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Self-Repairing Digital System Based on State Attractor Convergence Inspired by the Recovery Process of a Living Cell

Source Code Error Detection in High-Level Synthesis Functional Verification

Squaring in Reversible Logic using Zero Garbage and Reduced Ancillary inputs

Using Tweaks To Design Fault Resistant Ciphers

A High Throughput List Decoder Architecture for Polar Codes

Design and Analysis of Inexact Floating-Point Adders

Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers

Hybrid LUT/Multiplexer FPGA Logic Architectures

Low-Power Parallel Chien Search Architecture Using a Two-Step Approach

Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression

Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design

Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding

VLSI Design for Convolutive Blind Source Separation

A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler

A Generalization of Addition Chains and Fast Inversions in Binary Fields

A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications

A parallel radix-sort-based VLSI architecture for finding the first W maximum/minimum values

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability